1. Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including means for repairing the memory device with respect to possible defective memory portions.
2. Background of Art
FIG. 10 shows in a block diagram the structure of a conventional erasable and programmable read only memory (EPROM). As shown therein, a memory cell array 100 includes a data memory region 1 and a code memory line 2. As shown in FIG. 11, the memory cell array 100 includes a matrix of a plurality of word lines WL and a plurality of bit lines BL. A memory cell MC is provided at each intersection of the word and bit lines. In FIG. 10, the memory cell array 100 is divided into 16 memory cell blocks BK. A Y gate section 3 includes a plurality of Y gates corresponding to the memory cell array blocks BK. Similarly, a data input/output section 4 includes a plurality of data input/output circuits 40 corresponding to the memory cell array blocks BK.
An address input circuit 5 is supplied with address signals from outside. An X-decoder 6 is supplied with X address signals from the address input circuit 5 and a Y decoder 7 is supplied with Y address signals from the address input circuit 5. Responsive to the X address signals, the X decoder 6 selects one of the word lines WL in the memory cell array 100 and, responsive to the Y address signals, the Y decodes 7 selects one of the bit lines BL in each of the memory cell blocks BK. The Y gates 30 connect the bit lines BL selected in the corresponding memory cell array blocks BK to the corresponding data input/output circuits 40. Memory cells MC which is provided at the intersection of the selected word line WL and bit lines BL selected in this manner are selected.
During data read-out, data D0 to D15 are read out from the thus selected 16 memory cells MC via the Y gate section 3 and the data input/output section 4. Similarly, during data writing, the data D0 to D15 are written into the thus selected 16 memory cells MC via the data input/output section 4 and the Y gate section 3.
On the other hand, a control circuit 8 operates responsive to various control signals supplied from outside, such as CE, OE or PGM, to produce various timing signals to control the operation of various portions of the EPROM.
Each memory cell MC in the memory cell array 100 is comprised of the memory transistor such as one shown in FIG. 12. The memory transistor is comprised of N.sup.+ layers of a source 22 and a drain 23, formed on a P type semiconductor substrate 21, a floating gate 24 and a control gate 25.
During data programming, a source potential V.sub.pp of an electrical source for programming is applied to the control gate 25. The source potential V.sub.pp of the electrical source for programming is set to 12.5 V. At this time, the source 22 and the drain 23 are set to 0 V and about 8 V, respectively. During data read-out, a source potential V.sub.cc is applied to the control gate 25. At this time, the source 22 is at 0 V and the drain 23 is at about 1 V. The source potential V.sub.cc is usually set to 5 V.
FIG. 13 shows the relation between the drain current I.sub.D and the gate voltage V.sub.G of the control gate of the memory transistor. In this memory transistor, data "0" or "1" are stored, depending on whether or not electrons are stored in the floating gate 24 of the transistor. More in detail, when the electrons are stored in the floating gate 24 as a result of the programming operation, the threshold voltage of the memory transistor is raised. This causes a non-conductive state to be established between the source 22 and the drain 23 on application of a read-out voltage V.sub.R to the control gate 25. This state indicates that data "0" is stored in the memory transistor. Conversely, when the electrons are extracted from the floating gate 24 as a result of the erasure operation, the threshold voltage of the memory transistor is lowered. This causes a conductive state to be established between the source 22 and the drain 23 on application of a read-out voltage V.sub.R to the control gate 25. This state indicates that a data "1" is stored in the memory transistor.
Referring to FIG. 10, the manufacturer's code and the device codes are stored in the code memory line 2 of the memory cell array 100. These manufacturer's codes and the device codes are usually employed for automatic recognition of the programming setting conditions adopted in a programming apparatus adapted to program data in the EPROM. More in detail, since the data programming systems and the programming voltages differ from one manufacturer of the EPROM to another and from one device to another, the manufacturer's codes and the device codes may be advantageously employed to effect automatic setting required for programming by the programming apparatus.
The operation of reading out the manufacturer's codes and the device codes stored in the code memory line 2 will be explained. When a high potential of approximately 12 V is applied to an address input terminal adapted to be supplied with an address signal A9, a high voltage input detecting circuit 9 is activated. This causes the code memory line 2 adapted to store the manufacturer's code and the device code to be selected, while causing the non-selected state to be established in the X-decoder 6. As a result, the manufacturer's code or the device code stored in the memory cells constituting the code memory line 2 are outputted to the outside via the bit lines, Y gate section 3 and the data input/output section 4. When the address signal A0 is at a low (L) level, the EPROM's manufacturer's code is outputted and, when the address signal A0 is at a high (H) level, the device code of the particular EPROM is outputted.
It will be noted that flaws or defects may be caused in the memory cell array in the course of the manufacture process of the above described semiconductor memory device. For remedying the failure caused by these defects and thereby improving the yield, semiconductor memory device having redundancy circuits have become popular. However, with the recent increase in the capacity of the semiconductor memory device and the chip size, it is feared that there may be a certain limitation to the increase in the yield despite provision of the redundancy circuits.
In this view, there has been evolved a semiconductor memory device in which, when certain memory cell or cells are defective, the defective memory cell or cells are put out of use so that the memory device can be used as a memory device of a small memory capacity. The semiconductor memory device of this type is described for example in the Japanese Patent Laying-Open Gazette Nos. 40392/1984 and 501564/1983. The Japanese Patent Laying-Open Gazette No. 40392/1984 discloses a technique in which only one half area of the memory is used by fixing the address data to "1" or "0" to repair the defective memory chips. On the other hand, the Japanese Patent Laying-Open Gazette No. 501564/1983 discloses a technique in which one half memory area is used by designating an address code to repair to the defective memory chips.
Each of the prior art semiconductor memory devices can be used as a memory having one half the memory area when certain portions thereof are defective.
However, in the above described prior art semiconductor memory devices, the situation is that memory chips the total memory region of which can be used and the memory chips one half memory region of which can be used exist randomly on one and the same wafer. It would be difficult and lower the operating efficiency if, at the time of packaging of these memory chips, the memory chips need be checked as to whether the totality of the memory region or one half memory region thereof may be used in order to package them in the distinct packages.
Moreover, since the chip having the totality of the memory area usable and the chip having one half memory area usable present the same appearance, it is impossible to make automatic distinction between the chips the totality of the memory area of which is usable and the chips one half memory area of which is usable.